1Learning Outcomes¶
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2Tracing the add Datapath¶
3Arithmetic Logic Unit (ALU)¶
In the previous chapter we implemented a basic four-operation ALU. In the full RISC-V implementation, our ALU (Figure 1) must support all operations for R-Type instructions:
Figure 1:ALU Block.
Table 1:Signals for ALU Block
| Name | Direction | Bit Width | Description |
|---|---|---|---|
A | Input | 32 | Data to use for Input A in the ALU operation |
B | Input | 32 | Data to use for Input B in the ALU operation |
ALUSel | Input | 4 | Selects which operation the ALU should perform (see Table 2) |
ALUResult | Output | 32 | Result of the ALU operation |
3.1Course Project Details¶
Below, we detail the ALU operations that must be implemented for the course project’s datapath. We encourage revisiting this section after reading a few more example datapath traces.
Table 2:Operations for ALU Block for the course project
| ALUSel Value (for Project) | Operation | ALU Function |
|---|---|---|
| 0 | add | ALUResult = A + B |
| 1 | sll | ALUResult = A << B[4:0] |
| 2 | slt | ALUResult = (A < B (signed)) ? 1 : 0 |
| 3 | Unused | - |
| 4 | xor | ALUResult = A ^ B |
| 5 | srl | ALUResult = (unsigned) A >> B[4:0] |
| 6 | or | ALUResult = A | B |
| 7 | and | ALUResult = A & B |
| 8 | mul | ALUResult = (signed) (A * B)[31:0] |
| 9 | mulh | ALUResult = (signed) (A * B)[63:32] |
| 10 | Unused | - |
| 11 | mulhu | ALUResult = (A * B)[63:32] |
| 12 | sub | ALUResult = A - B |
| 13 | sra | ALUResult = (signed) A >> B[4:0] |
| 14 | Unused | - |
| 15 | bsel | ALUResult = B |
Observations/reminders:
When performing shifts, only the lower 5 bits of
Bare needed, because only shifts of up to 32 are supported.The comparator component might be useful for implementing instructions that involve comparing inputs. See the branch implementation later in this chapter.
A multiplexer (MUX) might be useful when deciding between operation outputs (recall our basic 4-operation ALU). Consider first processing the input for all operations first, and then outputting the one of your choice.
(sec-general-multiplication)
3.2General Multiplication¶
An ALU that implements the mul, mulh, and mulhu instructions can support parts of the RISC-V “M” extension.
| Instruction | Name | Description | Type | Opcode | Funct3 | Funct7 |
|---|---|---|---|---|---|---|
mul rd rs1 rs2 | MULtiply | R[rd] = (R[rs1] * R[rs2])[31:0] | R | 011 0011 | 000 | 000 0001 |
mulh rd rs1 rs2 | MULtiply Higher Bits | R[rd] = (R[rs1] * R[rs2])[63:32] (Signed) | R | 011 0011 | 0001 | 000 0001 |
mulhu rd rs1 rs2 | MULtiply Higher Bits (Unsigned) | R[rd] = (R[rs1] * R[rs2])[63:32] (Unigned) | R | 011 0011 | 011 | 000 0001 |
The result of multiplying 2 32-bit numbers can be up to 64 bits of information, but we’re limited to 32-bit data lines, so mulh and mulhu are used to get the upper 32 bits of the product. The Multiplier component has a Carry Out output (with the description “the upper bits of the product”) which might be particularly useful for certain multiply operations.